Article 403 of comp.sys.apple2.programmer: Newsgroups: comp.sys.apple2.programmer Path: caen!uwm.edu!cs.utexas.edu!uunet!tarpit!bilver!vicstoy!aphelps From: aphelps@vicstoy.UUCP (Austin Phelps) Subject: Re: SSC info wanted (again) Message-ID: <1993Jul17.170858.2473@vicstoy.UUCP> Organization: vicstoy public access Unix, Orlando, FL References: <199307152147.AA18084@ghostwheel.bga.com> Date: Sat, 17 Jul 1993 17:08:58 GMT Lines: 41 In article <199307152147.AA18084@ghostwheel.bga.com> khym@ghostwheel.bga.com (Dave Huang) writes: >I was wondering, what do $C088 + n0 through $C08B + n0 on a Super >Serial Card do? Address Register Bits Interpretation $C081+n0 DIPSW1 0 SW1-6 is OFF when 1, ON when 0 (SW1-x) 1 SW1-5 is OFF when 1, ON when 0 4-7 Same as above for SW1-4 through SW1-1 $C082+n0 DIPSW2 0 Clear to Send (CTS) is true when 0 (SW2-x) 1-3 Same as above for SW2-5 through SW2-3 5,7 Same as above for SW2-2 and SW2-1 $C088+n0 TDREG 0-7 ACIA transmit register (write) RDREG 0-7 ACIA receive register (read) $C089+n0 STATUS ACIA status/reset register 0 Parity error detected when 1 1 Framing error detected when 1 2 Overrun detected when 1 3 ACIA receive register full when 1 4 ACIA transmit register empt when 1 5 Data Carrier Detect (DCD) true when 0 6 Data Set Ready (DSR) true when 0 7 IRQ has occured when 1 $C08A+n0 COMMAND ACIA Command register (r/w) 0 DTR - enable (1) or disable (0) receiver and all IRQ 1 When 1 allow STATUS bit 3 to cause IRQ 2-3 Control transmit interrupt, RTS level and transmitter 4 0=normal mode for receiver, 1=echo mode-bit2,3 must be 0 5-7 Control Parity $C08B+n0 Control ACIA control register (r/w) 0-3 baud rate $00=16 x external clock 4 1=use baud rate generator; 0=use external clock (ns) 5-6 # of data bits 7 # of stop bits -- Austin Phelps - aphelps@vicstoy.oau.org -or- tf3@delphi.com UUCP - {peora,ge-dab,tous,tarpit}!bilver!vicstoy!aphelps - vicstoy Public Access Unix, Orlando FL - (407)299-3661 1200/2400/9600 V.32 24 hours 8N1